1. Field of the Invention
This invention relates to SRAM cells and more particularly to a process for fabrication thereof.
2. Description of Related Art
U.S. Pat. No. 5,057,893 of Sheng et al for "Static RAM Cell with Soft Error Immunity" shows the use of a second spacer on some devices.
FIG. 1 shows a prior art SRAM (Static Random Access Memory) device 6 with a substrate 10 composed of silicon having formed thereon a symmetrical LDD (Lightly Doped Drain) device. The device includes a gate oxide layer 14 upon which a polysilicon gate 15 is formed with spacers 20 on either side. Beneath the spacers 20 are N- doped regions 13 and 11 in the Source and Drain regions of the device. Aside from the spacers 20 and N- doped regions 13 and 11 are N+ doped regions 23 and 12 which have higher concentrations of dopant added after the N- dopant has been implanted and the spacers 20 have been formed.
FIG. 2 shows a prior art device 7 with a substrate 30 composed of silicon having formed thereon an asymmetrical LDD (Lightly Doped Drain) including a gate oxide layer 34 upon which a polysilicon gate 36 is formed with spacers 40 on either side. Beneath only the right side spacer 40 is an N- doped region 31 in the Drain region of the device. Aside from the spacers 40 and the N- doped regions 31 are N+ doped regions 43 and 42, which have higher concentrations of dopant added after the N- dopant has been implanted and the spacers 40 have been formed.
The Idsat of the Symmetrical LDD Structure is reduced (suffers) from about 10% to about 50% depending upon the source side N- concentration. The asymmetrical LDD with N+ on the source side can improve (increase) Idsat without any sacrifice in device performance (i.e. breakdown voltage, snapback voltage, Hct e- Reliability, etc.)
Using an asymmetric LDD Device in an SRAM Memory Cell, as shown in FIG. 2, one extra mask is used to open the source side of the drive device, then using an N+ (i.e. 1El5 As.sup.+) implant, improves the cell ratio from about 20% to about 40% or can reduce cell size with the same cell ratio.
The cell ratio (current) is defined as follows: ##EQU1## An example is shown in FIG. 7. In the polysilicon load SRAM cell this ratio is typically kept around 3 for cell stability, and the larger the value, the better. If one increases the device current, the cell ratio will increase, so then one can reduce the width of the drive device while keeping the same cell ratio R.sub.c.
FIG. 3 shows a prior art device with a substrate 10 composed of silicon with the device comprising a symmetrical LDD (Lightly Doped Drain) including a gate oxide layer 14 upon which polysilicon gates 15 and 16 are formed with spacers 20 on either side. Beneath the spacers 20 are N- doped regions 11, 12 and 13 in the Source and Drain regions of the device. Aside from the spacers 20 and N- doped regions 11, 12 and 13 are N+ doped regions 23 and 12 which have higher concentrations of dopant added after the N- dopant has been implanted and the spacers 20 have been formed. For example, sub-half-micron spacers will block N+ S/D implants or increase S/D resistance.
A problem is illustrated by FIG. 3, which is based on a case in which cell geometry has become far smaller to the extent that the oxide spacer blocks the N+ S/D implant thereby dramatically increasing the S/D resistance. As in FIG. 8B, T3 and T7 spacing will be too small, the spacer will block the N+ S/D implant, and increase the S/D resistance. The increased source resistance Ry (Rz) in FIG. 7 will impact cell stability as shown in FIG. 6 of "A New Process Technology for a 4 Mbit SRAM with Polysilicon Load Resistor Cell" K. Yuzuriha et al, Symposium on VLSI Technology, pp 61-62 (1989), so a ground resistance as low as possible is required.
The process of formation of a device of the kind shown in FIG. 3 is described here to illustrate the problem of providing an adequate level of dopant in the space between adjacent gate elements 15 and 16, in more detail.
FIG. 4 shows a device in accordance with this invention.
FIGS. 5A-5C illustrate a prior art process of making a device similar to the device shown in FIG. 3 and FIGS. 6A-6D illustrate the process of making a device similar to the device shown in FIG. 4. Moreover, the process steps shown in FIGS. 6A-6D show a process in accordance with this invention which is modification of the process shown in FIGS. 5A-5C.
In brief, FIG. 5A shows the results of the preliminary set of steps of manufacture of a device similar to the device of FIG. 3, with corresponding elements having similar reference numbers to those in FIG. 3. FIG. 5A shows the device, after the gate oxide layer 14 was formed, an N- ion implant process was performed resulting in identical structures. FIG. 6A shows the result of the preliminary set of steps of manufacture of a device of the kind shown in FIG. 4, which is an alternative process to that used to produce the device of FIG.3 Ions 17 have been implanted in silicon semiconductor substrate 10 forming N- regions 11, 12, and 13 in FIG. 5A and ions 37 have been implanted in silicon semiconductor substrate 30 forming N- regions 31, 32, and 33 in FIG. 6A.
In FIG. 6B, a photoresist mask 38 has been applied over the device of FIG. 6A, but in accordance with this invention as illustrated in FIG. 6B, the mask 38 has been patterned with and opening 29 on the source side of the device for an N+ ion implant step as illustrated with ions 39 being implanted therein.
To produce the product of FIG. 5B from the device of FIG. 5A, a CVD deposit of silicon dioxide layer 20 is made followed by a spacer etchback leaving the silicon dioxide spacers 20 shown in FIG. 5B. In an identical process, the product of FIG. 6C is produced from the device of FIG. 6B, a CVD deposit of silicon dioxide layer 40 is made followed by a spacer etchback leaving the silicon dioxide spacers 20 shown in FIG. 5B.
To produce the product of FIG. 5C from the device of FIG. 5B, an N+ implant of arsenic (As) ions 19 has been made thereon. To produce the product of FIG. 6D from the device of FIG. 6C, an N+ implant of As ions 59 has been made thereon producing an asymmetric device as can be seen by comparison of the regions 24 and 44 in the source sides of the devices of FIGS. 5C and 6D.
The prior art process comprises the steps as follows:
Form a gate oxide layer 14 on a silicon semiconductor substrate 10, as is well known to those skilled in the art.
Form a polysilicon layer for gate structures 15 and 16 on the gate oxide layer by forming a polysilicon layer on the gate oxide layer.
Form a mask for polysilicon gate structures by use of photolithography
Perform an etching processes in accordance with the art, as shown in FIG. 5A to form the gate structures 15 and 16 from the polysilicon layer.
Perform an N- ion implantation of phosphorous (P) ions 17 into said substrate 10 in all areas exposed adjacent to the polysilicon structures 15 and 15 forming N- regions 13, 12 and 11, as shown in FIG. 5A.
Form an N+ photoresist mask 18 on the device of FIG. 5A.
Referring again to U.S. Pat. No. 5,057,893, there is no ion implantation step. In addition there is no step of application of a mask at this stage in prior art processes.
Perform a CVD silicon dioxide deposition of layer 20 over the device covering the polysilicon gates 15 and 16, etc.
Etch the silicon dioxide layer 20 to form spacers therefrom, with the remainder of the silicon dioxide being removed as is well known to those skilled in the art leaving the structure shown in FIG. 4, with the gate oxide layer etched away by the spacer layer etchant where the spacer layer 20 has been removed.
Perform an N+ implantation of As ions 19 into said substrate 10 in all areas exposed adjacent to the polysilicon structures 15 and 16 and spacer structures 20 forming N+ regions 23, 24 and 22, as shown in FIG. 5C.